As discussed in Part 1 of our ADC Topology Series, Analog-to-Digital converters (ADCs) are used as an interface element between the analog and digital worlds to convert an analog input into a corresponding digital output.
There is a continuing trend in the industry toward achieving higher data throughput in both wired and wireless digital communication systems. This trend results in increasingly more demanding requirements from ADCs in terms of sampling rate and conversion accuracy. Meeting these specifications requires the use of different ADC topologies. One such topology is the Dual-Slope ADC.
Overview of Dual-Slope ADCs
The dual-slope ADC architecture was a breakthrough in ADCs for high-resolution applications such as digital voltmeters (DVMs). The dual-slope ADC has the following advantages:
- Noise present on the input voltage is reduced by averaging
- The values of the capacitor and conversion clock do not affect conversion accuracy since they act equivalently on the up-slope and down-slope
- Linearity is very good and extremely high-resolution measurements can be obtained
Its main disadvantage is a slow conversion rate, often in the range of 10 samples/second. In applications where this is not a problem, such as in measuring temperature transducers, a dual-slope ADC is a good choice.
In a dual-slope ADC as shown in Figure 1, the input signal is applied to an integrator. At the same time, a counter begins counting clock pulses. After a predetermined amount of time (T), a reference voltage with opposite polarity is applied to the integrator. At that instant, the accumulated charge on the integrating capacitor is proportional to the average value of the input over the interval T as shown in Figure 2. The integral of the reference is an opposing ramp with a slope of VREF/RC. Simultaneously, the counter is again counting from zero. When the integrator output reaches zero, the counter stops, and the analog circuitry is reset. Since the charge gained is proportional to VIN × T, and the equal amount of charge lost is proportional to VREF × tx, then the number of counts relative to the full-scale count is proportional to tx/T, or VIN/VREF. If the output of the counter is a binary number, it will therefore be a binary representation of the input voltage.
Figure 1. Dual Slope ADC Architecture
Figure 2. Dual Slope ADC Operation
Vidatronic has several data converter IP blocks that offer flexible and efficient analog-to-digital and digital-to-analog conversion at different speeds to cover customers’ needs. Vidatronic has an 8-bit Dual Slope ADC designed in a 180 nm process suitable for digitizing slow moving analog sensor signals in low-power battery-operated systems. This ADC IP has an integrated 32-input channel multiplexer for monitoring various signals. The ADC auto-calibrates for offset and gain error and achieves 8-bit ENOB measurement resolution. Vidatronic data converters are silicon proven in several silicon processes and can be ported to any process required by our customers.
This blog post is part of a series. You can view the other posts in the series below.
Part 1: Analog-to-Digital Converter Topologies: SAR ADCs
Part 2: Analog-to-Digital Converter Topologies: Flash ADCs
Part 3: Analog-to-Digital Converter Topologies: Pipeline ADCs
Part 4: Analog-to-Digital Converter Topologies: Sigma-Delta ADCs
To learn more about ADCs, check out our full white paper on the different ADC topologies and their applications: