Analog-to-Digital converters (ADCs) are used as an interface element between the analog and digital worlds to convert an analog input into a corresponding digital output. ADCs are currently used in many application fields to improve digital systems, which can achieve superior performance compared to analog solutions.
Some examples of situations where ADCs are necessary include:
- When data from the analog domain, through sensors or transducers, should be digitally processed.
- When transmitting data between chips through long range wireless radio links in high speed wireline transceivers between chips either on the same printed circuit board (PCB) or in a multi-die module.
- When used in analog test equipment (ATE) testing.
There is a continuing trend in the industry toward achieving higher data throughput in both wired and wireless digital communication systems. This trend results in increasingly more demanding requirements from ADCs in terms of sampling rate and conversion accuracy. There are many applications for ADCs, each requiring specific specifications. Meeting these specifications requires the use of different ADC topologies. One such topology is the Successive-Approximation-Register (SAR) ADC.
Overview of SAR ADCs
SAR ADCs represent the majority of the ADC market for medium- to high-resolution ADCs. SAR ADCs provide up to 12Msps sampling rates with resolutions from 8 to 18 bits.
As shown in the SAR ADC architecture illustrated in Figure 1, the sample and hold (S&H) block samples the continued input voltage (Vin) and the comparator block then compares the sampled input with the DAC voltage from the SAR logic. The SAR logic puts out a binary code to the DAC for each bit, which depends on the current bit that is under consideration of the already approximated previous bits. The status of the current bit is determined by using the comparator. The digital output is generated at the end of conversion (EOC), after all bits have been approximated.
Figure 1. SAR ADC Architecture
Vidatronic offers a flexible 10-bit SAR ADC/DAC combination IP in GLOBALFOUNDRIES 22 nm FDSOI process. This IP is a part of our 22 nm Low-Power Analog Security IP Series that has been optimized for integration into Systems-on-a-Chip (SoCs) and designed to aid in physical attack mitigation on SoCs.
This blog post is part of a series. You can view the other posts in the series below.
Part 2: Analog-to-Digital Converter Topologies: Flash ADCs
Part 3: Analog-to-Digital Converter Topologies, Pipeline ADCs
Part 4: Analog-to-Digital Converter Topologies: Sigma-Delta ADCs
Part 5: Analog-to-Digital Converter Topologies: Dual-Slope ADCs
To learn more about ADCs, check out our full white paper on the different ADC topologies and their applications: